Rate 1/2, Constraint Length 3 Encoder (K=3, g1=[1,1,1], g2=[1,0,1])
Shift Register: Input bits shift through K-1 memory cells. Current output depends on current and past inputs.
Generator Polynomials: g1=[1,1,1] and g2=[1,0,1] define which taps connect to each output via XOR.
Rate 1/2: For every 1 input bit, we get 2 output bits. More redundancy = better error correction!
Constraint Length K: Determines memory. Longer K = better performance but more complex decoder.
Decoding: Viterbi algorithm finds most likely path through code trellis.
Applications: Deep space (Voyager), GSM, satellite, Wi-Fi (802.11a/g/n).